A typical wiring schematic of a memory chip, e.g., a DRAM chip, is shown in FIG. 1. In this wiring schematic, the interface logic and I/O (input/output) circuits are placed near the IC pad-row and, as a result, those circuits can have a good power connection. On the other hand, the array control logic circuits are placed somewhere between memory arrays and memory banks. FIG. 2 shows an example of a more detailed view of these array control logic circuits. Since these array logic circuits are placed in between the memory arrays, they require much longer wiring connections in order to establish connections to the corresponding IC pads. The array control logic block and interface logic block are connected via multi digit buses containing the high data-rate bidirectional data buses, which can transfer the read and write data. Further, the array control logic block and interface logic block are also connected via what is so-called as ‘the configuration buses,’ which can carry the low data rate, or even static signals. These static signals can comprise test-mode signals, redundancy information, or some customer specific setting information for the memory arrays, which can be configured during the chip initialization period.
The state-of-art technology for integrated circuits (IC) can impose a limit on the maximum number of metal layers which can be placed in a memory chip, e.g., a DRAM chip. The limit is often associated with the production cost and the chip area budget. First, placing any additional metal layers in a chip increases the production cost per chip, which is often undesirable in this current market for the integrated circuits. This is often undesirable in this current market for memory chips where the smaller-sized memory chips are preferred over the bigger-sized memory chips.
One way to minimize the number of metal layers to be used in a chip as well as the planar area of the chip is to configure the data bus/power wirings so that the data buses and power supply wires share the same metal layer/plan. FIG. 3 shows an example of a bus-system schematic where the data buses and power supply wires share the same metal layer/plane. The dashed arrows represent a return current, which will be explained in more detail later.
An exemplary schematic with an additional metal layer is shown in FIG. 4. The dashed arrows represent a return current. In this case, the area of the current return loop becomes much larger than in the case where the data bus wires and power supply wires share the same metal plane/layer, as shown in FIG. 3. Further, the return current can interact with different signals and cause undesirable magnetic/electric couplings. In fact, all the return currents are summed in a relatively narrow supply wire, which may cause parasitic coupling.
Accordingly, the chip schematic where the data bus wires and power supply wires share a common metal plane/layer, as shown in FIG. 3, is preferred over the chip schematic where the power supply wires are placed in an additional, separate metal plane/layer from the data bus wires, as shown in FIG. 4.
However, the chip schematic shown in FIG. 3, where the data buses and power supply wires share a common metal layer/plane may entail several problems—e.g., first is a problem of cross-talk between neighbouring data wires and mutual influence via shared power supply wires, and second is a problem of voltage drop/voltage glitch on power supply wires. Each of these problems is explained in more detail.
The cross-talk between neighbouring wires and the voltage drop on power supply wires are caused by a parasitic power balance, in other words, parasitic couplings through the power network. FIG. 5 shows an example of an interface including one driver inverter, one receiving inverter, power supply wires VDD and VSS and data wires. The parasitic, capacitive couplings are represented by the wire-to-wire capacitors shown in FIG. 5.
However, the parasitic capacitance does not form only between the neighbouring wires. In addition, the parasitic capacitance can form between part-to input (gate-to-source and gate-to-bulk) of the transistors belonging to either the driver inverter or receiver inverter. All these parasitic capacitances that form between wire-to-wire electric fields, part-to-input (gate-to-source and gate-to-bulk) electric fields can add up to further exacerbate the voltage-drop problem in the power wires in a memory chip. However, for simplicity purposes, these parasitic capacitances are not illustrated in FIG. 5.
Specifically, when the data wire changes the voltage state from VDD to VSS or VSS to VDD, the parasitic capacitors shown in FIG. 5 will be re-charged. In other words every VSS to VDD or VDD to VSS transition on the data wire causes transient current flowing via data wire from transmitter to receiver, and then returning back through the supply wires. This current flowing through the parasitic capacitors causes the voltage drop in the supply wires. Since these parasitic virtual capacitors are created partly by the parasitic input capacitive couplings between the transistors of the receiving inverter and partly by the wire-to-wire and wire-to-substrate parasitic capacitive couplings, all of these capacitive couplings can exacerbate the voltage drop problem of the power supply wires.
The voltage drop problem is explained in more detail. FIGS. 6 and 7 show exemplary voltage drop/voltage glitches on the power supply wires, as caused by the parasitic capacitors as explained above.
First, FIG. 6 shows an example of the voltage drop/voltage glitch during a rising transition period of the input signal. Wires VDD and VSS represent power supply wires. Signal IN is input signal to driving inverter DI. Wire DW is data wire, and the voltage state of data wire DW is also illustrated. VDDout is the voltage output state of supply wire VDD, whereas VSSout is the voltage output state of supply wire VSS. DWout is the voltage output state of the data wire as outputted from receiving inverter RI. During a rising transition period, input signal IN changes the voltage state from a logical 0/low state to a logical 1/high state. Then, the transistors belonging to receiving inverter RI cause the parasitic virtual capacitors Cp to form, which results in a flow of current through those parasitic virtual capacitors, as represented by the dashed arrows in FIG. 6. This current is return current CR and is the main cause of the voltage drop/voltage glitch on the power supply wires, as shown by the glitches on VDDout and VSSout.
FIG. 7 shows an example of the voltage drop/voltage glitch problem during a falling transition period of the input signal. The reference numerals are the same as shown in FIG. 6 and thus not shown in FIG. 7. During a falling transition period, the input signal to the driving inverter falls from a logical 1/high state to a logical 0/low state. Then, the data wire placed in between driving inverter DI and receiving inverter RI changes the voltage state from a logical 0/low state to a logical 1/high state, as shown by the voltage state of data wire DW in FIG. 7. Then, parasitic virtual capacitors Cp are formed as explained above, which creates a flow of current through those parasitic virtual capacitors. This return current CR flowing through parasitic capacitors Cp are represented by the dashed line in FIG. 7. Similar to the case shown in FIG. 6, return current CR affect both power supply wires VDD and VSS, specifically causing the voltage drops/voltage glitches on power supply wires VDD and VSS, as represented by VDDout and VSSout in FIG. 7. Normally not only receivers are located on the far-end of data wire. On a memory chip array control circuitry includes different kind of address decoders, sense-amplifiers and so on. Mentioned circuits in operation are having relatively big current consumption, and this current also creates a voltage drop on supply wires.
Accordingly, it is desirable to mitigate the above identified problems—the problem of cross talk between neighbouring wires and the problem of voltage drop/voltage glitches on supply wires—to improve the power efficiency of a memory chip. The cross-talk between the wires can limit the data transmitting speed, whereas the voltage drop/voltage glitches on power supply wires can adversely affect the other circuits that are connected to the same power supply wires.
The above-identified problems—the problem of cross-talk between neighbouring wires and the problem of voltage drop/voltage glitch—can be improved 1) if a wider spacing is allowed between the data buses and power supply wires, 2) if an additional shielding wire is placed in between the sensitive wires, or 3) if a wider/larger wire having a larger cross-section is used for the power supply wires. A wider spacing can reduce the risk of a cross-talk between neighbouring wires, while placing a shielding wire in between the sensitive wires can have the same effect. Specifically, the parasitic capacitive couplings between the neighbouring, sensitive wires can be removed if the wires are placed far enough from each other on the conductive metal layer.
Further, using a wider/larger wire having a larger cross-section has a lower resistance and lower inductance than a narrower wire with a smaller cross-section. Thus, using a wider wire for the power supply wires can reduce the effective resistance and inductance for the power supply wires and thereby can improve the power integrity and signal to noise ratio.
However, the above three options may not be available in practice because of the rigid production cost budget and chip area budget. All of the options—allowing a wider spacing between the wires, adding a shielding wire in between the sensitive wires and using a wider wire for the power supply wires—can burden the chip area budget and make the size of a chip bigger. As explained above, increasing the size of a chip is often undesirable in this current market for ICs.
Furthermore, adding extra wires and using wider wires instead of narrower wires can burden the production cost because both the options are expensive. Especially, wider wires are usually more expensive than narrower wires because of area considerations. Therefore, all of the three options above may well turn out to be unavailable in the actual manufacturing practice.
Accordingly, it is desirable to be able to optimize the performance of a memory chip—i.e., mitigate the problem of cross-talk and the problem of voltage drop/voltage glitches on supply wires—by re-configuring the data bus wires and power supply wires without burdening the production cost budget and the chip area budget while still improving the performance of the power deliveries in the chip.